从零开始的RISC-V上的LED，计时器和中断（例如GD32VF103和IAR C ++）

今天，我们将讨论一种时尚的产品-RIS-V微控制器。我一直很想了解这个内核，并等待类似于STM32的出现，现在我等待，见面-中国的GigaDevice-GD32V。

该微控制器的基础设施不如STM32广泛，但您需要具备入门所需的一切。幸运的是，例如，可以在alikexpress上订购调试板，例如：Longan Nano GD32VF103CBT6 RISC-V MCU

中国人正在推广此微控制器的Platform IO开发环境，该环境可以作为Visual Studio Code的扩展提供。但是我们不会使用它，这不是根据工程概念，我们是工程师，我们想自己弄清楚它。因此，让我们尝试在IAR上运行该板，从头开始编写所有内容。

顺便说一下，IAR正在分发调试工具包（调试板+ I-Jet调试器+ 30天完整许可证）IAR RISC-V GD32V评估工具包。您可以在此处留下“开发工具请求”。不知道他们是否将工具包发送给所有人，但是我们在5天内收到了它。谢谢他们！

好吧，有兴趣的人，欢迎下切

介绍

CortexM, - IAR ( IAR ), , , .

— , . , , , , , , , , , , RISC-V , , , RISC-V .

, ( RISC-V). , , RISC-V.

RISC-V , , , . , , , , , , , .

RISC-V ( RISC-V, Syntacore), , , . , .

GD32VF103

, , - .

1. ISA RISC-V RISC-V :
   
   ISA
   
   ISA
2. GD32VF103. , . GD32VF103CBT6 — GD32 RISC-V Microcontroller
3. GD32VF103 Bumblebee, Nuclei processor core
4. ECLIC.
5. . .
6. Nuclei RISC-V , IAR n200 drivers
7. GigaDevice, IAR
8. FreeRTOS uCOS II n200 sdk
9. , Platform IO , . .

4 , ++ — , . :

100 200

RISC-V . , , RISC-V, :

• Hart ( ) — , . (hart) . (hart) ID 0. hart.
• Trap() — , . , — , — , , . :
  
  
  • (exception) — , . , NMI.
  • (interrupt) — , , . , NMI, .
  • (NMI) — . NMI NMI, NMI , NMI . , , , .
• Machine () — — , , . machine() . , , , .

… .

RISC-V

, :

RISC-V (-) — (ISA — Instruction Set Architecture) RISC . , . .

, , , :

, , . .

, 32 , :

:

• RV32: 32 16
• RV32I: 32 32

:

• M:
• C: 16
• :
• F:
• D:

— .

.

RISC-V 32 x0-x31. ABI .

:

t0-t6(x5-x7, x28-x31) a0-a7(x10-x17), . - , .

:

s0-s11 (x8, x9, x18-x27 ) ( ) , .

, , , :

.

x0/zero:

0 CSR( ), , CSRRS (Atomic Read and Set Bits in CSR), x0 , CSR . , CSR, , zero.

x1/ra:

(Link register Return Address ). . , , , ret, .

x2/sp:

. — . , CortexM, .

x3/gp:

(The global pointer register). (gp/x3) 4 .

gp, 4 , /pc- gp- , . .

4K , , , . .

x4/tp:

(The thread pointer). . (Thread Local Storage (TLS)), thread_local ++.

, — , .

, , , ISA, . :

.

, .. . : ISA

— , Linux, .

, , .

, . : ISA

, , . , , .

, - , .

RISC-V 3 . (, ). , , .

:

, , GD32VF103 M U. . U, , mtvt, mepc, . , , GD32VF103, .

.. M . — ecall — , , . mret — .

, , , , .

:

RISC-V, (, ).

GD32VF103

F GD32VF103 — , GD32F103 CortexM3. . , , - GD32F103 STM32F103 … GD32VF103 c GD32F103. ( , ), GD32F103, GD32VF103.

RV32IMAC — RISC-V 32- 32- , , 16 .

, :

• (Machine Mode), , .
• (User Mode), .

, . , . : Nuclei privileged ISA

4 :

• (Normal Mode — 0x0)
  
  , (NMI) .
• (Exception Handling Mode — 0x2)
  
  .
• (NMI Handling Mode — 0x3)
  
  NMI.
• (Interrupt Handling Mode — 0x1)
  
  .

TYP msumbm

0 ( ) , .

, , , , , . , , mret — , mstatus MPP , mepc. .

CSR (Control and Status Registers)

mstatus, mepc, msumbm, mtvt ..., ?

, , cssr csrr.

, , , - , .

, .

, . — , , IAR CSR . ( IAR, , GCC ).

 // Get    ,     ,   
 template<typename T = AccessMode,
        class = typename std::enable_if_t<std::is_base_of<ReadMode, T>::value ||
                                          std::is_base_of<ReadWriteMode, T>::value>>
 inline static Type Get()
 {
   return __read_csr(address) ;
 }

unsigned long get_mstatus()
{
  unsigned long value;
  asm volatile("csrr %0, 0x300" : "=r"(value));
  return value;
}

auto mstatus = get_mstatus() ;

auto mstatus = CSR::MSTATUS::Get() ;

, , , . CSR , x, xstatus — mstatus — , ustatus — . , , m , u .

.

, , . — .

mcause

. , .

mtvt2

- ECLIC .

msumb

Bumblebee, , .

mstatus

mstatus (hart). .

mmisc_ctl

, mnvec, NMI.

— 9 (NMI_CAUSE_FF). , 9 — , .

, NMI_CAUSE_FF( 9) 0x0, mnvec . 0x1, mnvec , mtvec, .. NMI , 0xFFF.

mepc

. . pc.

, RTOS .

mtvec

. , , mmisc_ctl

, . .

, 3 , .

• ( ),
• NMI( ),
• ( ).

-.

. Bumblebee :

:

— . RISC-V PLIC(Platform-Level Interrupt Controller) CLIC (Core-Local Interrupt Controller). PLIC , CLIC

PLIC mie and mip, RISC-V. , Linux.

CLIC. CLIC.

PLIC CLIC. CSR mtvec . (00b) PLIC - .

CLIC 11b. GD32VF103 ECLIC ( ) — CLIC,

:

4096 , , . , 19 , . ECLIC .

:

, / , , , , .

. , . 87 .

. , //NMI , :

• CSR
  
  
  • mcause
  • mepc
  • mstatus
  • mintstatus
• PC , — , NMI. .

, .

— , .

, .

, :

• , PC , mepc
• CSR :
  
  
  • mstatus
  • mcause
  • mintstatus
• , , .

.

RISC-V stacking unstacking CortexM , , 16 .

. — , - — . (, Interrupt Tail-Chaining) .

, , - . .

ECLIC — , . . , (- ). , , , . , . -.

, ( CortexM).

-

- . .. .

CLICINTATTR[i] SHV. 0 — - , .. , , mtvec mtvt2, .

, . , mcause — EXCCODE.

ECLIC

. 7 , , i — . .. 87 clicintip, 87 clicintie, 87 clicintattr 87 clicintctl, .

, , …

MTH

, . , , , - , , .

, clicintctl[i].

— mth. 8- , .

CLICINTCTL[i]

. , ( ), CLICCFG , — . CLICINFO CLICINTCTLBITS.

CLICCFG

. , . , .

? nlbits , .

CLICINFO

CLICINTIP[i]

. i — . 87 , 87 .

CLICINTIE[i]

. 87.

CLICINTATTR[i]

. , . , , . 87.

, , … .

— CortexM, . , (hart). mtime mtimecmp.

, CSR. , , .

. mtime 0xd1000000, mtimecmp 0xd1000008.

64 . :

• mtime —
• mtimecmp — . mtime mtimecmp CLICINTIP[7].

, , . , - , .

Writes to mtime and mtimecmp are guaranteed to be reflected in MTIP eventually, but not necessarily immediately.



A spurious timer interrupt might occur if an interrupt handler increments mtimecmp then immediately returns, because MTIP might not yet have fallen in the interim. All software should be

written to assume this event is possible, but most software should assume this event is extremely unlikely. It is almost always more performant to incur an occasional spurious timer interrupt than to poll MTIP until it falls.

, mtimecmp, mtime 0 , .

msip — . . RTOS , .

STM32, , . .

, Port control register 0 (GPIOx_CTL0, x=A..E).

Port output control register (GPIOx_OCTL, x=A..E), , .

svd , STM32. , .

… , , . . , . , ECLIC - .

, , mcause, mepc msubm, , , , . .

, , __interrupt, , , mret .

, stackless ++ … .

, .

__interrupt void IrqEntry()
{
  const auto mcause = CSR::MCAUSE::Get(); 
  const auto mepc = CSR::MEPC::Get(); 
  const auto msubm = CSRCUSTOM::MSUBM::Get(); 
  //    mcause
  const auto exceptionCode =  mcause & 0xFFF ; 
  //   
  NonVectoredInt::HandleInterrupt(exceptionCode); 

  __disable_interrupt();
  CSR::MCAUSE::Write(mcause); 
  CSR::MEPC::Write(mepc); 
  CSRCUSTOM::MSUBM::Write(msubm) ; 
}

-, ( , __interrupt), .

-, CSR , , , .

-, . , ( IAR).

namespace NonVectoredInt
{
  static void  HandleInterrupt(std::uint32_t interruptId)
  {
    // ,        
    assert(interruptId < InterruptVectorTable.size());
    //         
    tInterruptFunction fp = InterruptVectorTable[interruptId];
    if (fp != nullptr)
    {
      fp(); //  
    }
  }
} ;

, .

using tInterruptFunction = void(*)() ;

inline constexpr std::array<tInterruptFunction,87> InterruptVectorTable
{
  nullptr,
  nullptr,
  nullptr,
  DummyModule::HandleInterrupt,// 
  nullptr,
  nullptr,
  nullptr,
  SystemTimer::HandleInterrupt, //      
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  DummyModule::HandleInterrupt,//eclic_bwei_handler,
  DummyModule::HandleInterrupt, //eclic_pmovi_handler,
  DummyModule::HandleInterrupt, //WWDGT_IRQHandler,
  DummyModule::HandleInterrupt,//LVD_IRQHandler,
....
} ;

, 7 , , , SystemTimer::HandleInterrupt

struct SystemTimer
{
    static void HandleInterrupt()
    {
        auto mtime = MACHINETIMER::MTIME::Get() - 
                     MACHINETIMER::MTIMECMP::Get();
        MACHINETIMER::MTIME::Write(mtime);
        AppTimerService::OnSystemTick() ;        
    }
};

OnSystemTick() . , NMI.

, "". , 12.

inline constexpr std::array<tInterruptFunction,12> ExceptionVectorTable
{
  DummyModule::HandleInterrupt,  //0 - Instruction address misaligned
  DummyModule::HandleInterrupt,  //1 - Instruction access fault
  DummyModule::HandleInterrupt,  //2 - Illegal instruction
  DummyModule::HandleInterrupt,  //3 - Breakpoint
  DummyModule::HandleInterrupt,  //4 - Load address misaligned
  DummyModule::HandleInterrupt,  //5 - Load access fault
  DummyModule::HandleInterrupt,  //6 - Store/AMO address  misaligned
  DummyModule::HandleInterrupt,  //7 - Store/AMO access fault
  EnvironmentCall::HandleInterrupt,  //8 - Environment call from  U-mode
  nullptr,
  nullptr,
  EnvironmentCall::HandleInterrupt,  //11 - Environment call from  M-mode
};

namespace NonVectoredInt
{    
  static void  HandleException(std::uint32_t exceptiontId)
  {
    assert(exceptiontId < ExceptionVectorTable.size());
    tInterruptFunction fp = ExceptionVectorTable[exceptiontId];
    if (fp != nullptr)
    {
      fp();
    }
  }
} ;

NMI . — 0xFFF.

__interrupt void ExceptionEntry()
{
  const auto mcause = CSR::MCAUSE::Get();
  const auto mepc = CSR::MEPC::Get();
  const auto msubm = CSRCUSTOM::MSUBM::Get();

  const auto exceptionCode =  mcause & 0xFFF ;
  if (exceptionCode != 0xFFF) //   NMI
  {
    NonVectoredInt::HandleException(exceptionCode);
  } else
  {
    DummyModule::HandleInterrupt() ; //    NMI
  }

  __disable_interrupt();
  CSR::MCAUSE::Write(mcause); 
  CSR::MEPC::Write(mepc); 
  CSRCUSTOM::MSUBM::Write(msubm) ; 
}

, NMI , , mtvec, NMI 0xFFF, MMISC_CTL .

 //     NMI  , 
 //     mtvec.   NMI  0xFFF
 CSRCUSTOM::MMISC_CTL::NMI_CAUSE_FFF::MnvecIsMtvecNmiIsFFF::Set();

//     . 
// ,       MTVT2
CSRCUSTOM::MTVT2::Write(
           CSRCUSTOM::MTVT2::MTVT2EN::Mtvt2IsTrapAddress::Value |
           reinterpret_cast<std::uintptr_t>(&NonVectoredInt::IrqEntry));

a ECLIC NMI mtvec

 //      ECLIC      
 CSR::MTVEC::Write(
      CSR::MTVEC::MODE::Eclic::Value |
      reinterpret_cast<std::uintptr_t>(&NonVectoredInt::ExceptionEntry));        

… .

extern "C"
{
int __low_level_init(void)
{
 {
   CriticalSection cs;        
   //     NMI   , 
   //     mtvec.   NMI  0xFFF
   CSRCUSTOM::MMISC_CTL::NMI_CAUSE_FFF::MnvecIsMtvecNmiIsFFF::Set(); 

   //     . 
   // ,       MTVT2
   CSRCUSTOM::MTVT2::Write(
              CSRCUSTOM::MTVT2::MTVT2EN::Mtvt2IsTrapAddress::Value |
              reinterpret_cast<std::uintptr_t>(&NonVectoredInt::IrqEntry));

   //      ECLIC 
   //      
   CSR::MTVEC::Write(CSR::MTVEC::MODE::Eclic::Value |
       reinterpret_cast<std::uintptr_t>(&NonVectoredInt::ExceptionEntry));

   //       mycycle_minstret
   CSRCUSTOM::MCOUNTINHIBITPack<CSRCUSTOM::MCOUNTINHIBIT::IR::MinstretOn,
                CSRCUSTOM::MCOUNTINHIBIT::CY::McyclesOn
                >::Set();
   }
}

.

//         
//   CLICINTCTL_7.   3 
ECLIC::CLICCFG::NLBITS::MaxBitsForLevel3::Set();
//     0
ECLIC::MTH::Write<0U>();
//      
ECLIC::CLICINTATTR_7::SHV::NonVectored::Set();
//    1,    
ECLIC::CLICINTCTL_7::Write<
       1U << (8U - ECLIC::CLICCFG::NLBITS::MaxBitsForLevel3::Value)>();

//  .      1 .     
MACHINETIMER::MTIMECMP::MTIMEField::Value<SystemTimerPeriod>::Write() ;
MACHINETIMER::MTIME::Write<0U>();

//   -   7
ECLIC::CLICINTIE_7::IE::Enable::Write();

//   
CSR::MSTATUSPack<CSR::MSTATUS::MIE::InterruptEnabled>::SetValueBitsAtomic();

, . GPIOC.7 GPIOB.6

RCU::APB2EN::PCEN::Enable::Set(); 
RCU::APB2EN::PBEN::Enable::Set();
GPIOC::CTL0::CTLMD7::GpioOutputPushPull50Mhz::Set();
GPIOB::CTL0::CTLMD6::GpioOutputPushPull50Mhz::Set();

#include "gpiocregisters.hpp"
#include "gpiobregisters.hpp"
#include "rcuregisters.hpp"  //for RCU
#include "csrregisters.hpp" //for CSR
#include "eclicregisters.hpp" // for ECLIC
#include "machinetimerregisters.hpp"
#include "systemconfig.hpp" // for SystemTimerPeriod
#include "criticalsection.hpp" // for CriticalSection
#include "csrcustomregisters.hpp"
#include "vectortable.hpp" //for InterruptVectorTable

namespace NonVectoredInt
{
    static void HandleInterrupt(std::uint32_t interruptId)
    {
        assert(interruptId < InterruptVectorTable.size());
        tInterruptFunction fp = InterruptVectorTable[interruptId];
        if (fp != nullptr)
        {
            fp();
        }
    }

    static void HandleException(std::uint32_t exceptiontId)
    {
        assert(exceptiontId < ExceptionVectorTable.size());
        tInterruptFunction fp = ExceptionVectorTable[exceptiontId];
        if (fp != nullptr)
        {
            fp();
        }
    }

    __interrupt void ExceptionEntry()
    {
        const auto mcause = CSR::MCAUSE::Get();
        const auto mepc = CSR::MEPC::Get();
        const auto msubm = CSRCUSTOM::MSUBM::Get();
        const auto exceptionCode = mcause & 0xFFF;

        if (exceptionCode != 0xFFF) // if not NMI
        {
            NonVectoredInt::HandleException(exceptionCode);
        }
        else
        {
            DummyModule::HandleInterrupt(); // for NMI handling
        }

        __disable_interrupt();
        CSR::MCAUSE::Write(mcause);
        CSR::MEPC::Write(mepc);
        CSRCUSTOM::MSUBM::Write(msubm);
    }

    __interrupt void IrqEntry()
    {
        const auto mcause = CSR::MCAUSE::Get();
        const auto mepc = CSR::MEPC::Get();
        const auto msubm = CSRCUSTOM::MSUBM::Get();
        const auto exceptionCode = mcause & 0xFFF;

        NonVectoredInt::HandleInterrupt(exceptionCode);

        __disable_interrupt();
        CSR::MCAUSE::Write(mcause);
        CSR::MEPC::Write(mepc);
        CSRCUSTOM::MSUBM::Write(msubm);
    }
}

extern "C"
{
int __low_level_init(void)
{
    {
        CriticalSection cs;

        //     NMI   , 
        //     mtvec.   NMI  0xFFF
        CSRCUSTOM::MMISC_CTL::NMI_CAUSE_FFF::MnvecIsMtvecNmiIsFFF::Set(); 

        //     . 
        // ,       MTVT2
        CSRCUSTOM::MTVT2::Write(
                   CSRCUSTOM::MTVT2::MTVT2EN::Mtvt2IsTrapAddress::Value |
                   reinterpret_cast<std::uintptr_t>(&NonVectoredInt::IrqEntry));

        //      ECLIC   
        //    
        CSR::MTVEC::Write(
                    CSR::MTVEC::MODE::Eclic::Value |
                    reinterpret_cast<std::uintptr_t>(&NonVectoredInt::ExceptionEntry));

        //       mycycle_minstret
        CSRCUSTOM::MCOUNTINHIBITPack<CSRCUSTOM::MCOUNTINHIBIT::IR::MinstretOn,
                                     CSRCUSTOM::MCOUNTINHIBIT::CY::McyclesOn
                                    >::Set();
    }
    ECLIC::CLICCFG::NLBITS::MaxBitsForLevel3::Set();

    //     0
     ECLIC::MTH::Write(0U);
    //      
     ECLIC::CLICINTATTR_7::SHV::NonVectored::Set();

    //    1,    
    ECLIC::CLICINTCTL_7::Write<
           1U << (8U - ECLIC::CLICCFG::NLBITS::MaxBitsForLevel3::Value)>();

    MACHINETIMER::MTIMECMP::MTIMECMPField::Value<SystemTimerPeriod>::Write() ;
    MACHINETIMER::MTIME::Write<0U>();

    //   -   7
    ECLIC::CLICINTIE_7::IE::Enable::Write();

    //Enable machine interrupt
    CSR::MSTATUSPack<CSR::MSTATUS::MIE::InterruptEnabled>::SetValueBits();

    RCU::APB2ENPack<RCU::APB2EN::PCEN::Enable,
                    RCU::APB2EN::PBEN::Enable>::Set();
    GPIOC::CTL0::CTLMD7::GpioOutputPushPull50Mhz::Set();
    GPIOB::CTL0::CTLMD6::GpioOutputPushPull50Mhz::Set();

    return 1;
}
}

int main()
{
    while (true)
    {
        asm volatile(" ");
    }

    return 0;
}

.

, . . OnTick()

template<typename ...Timers>
struct TimerService
{
  static void OnSystemTick()
  {
    (Timers::OnTick(), ...);
  }
};

— , OnTimeout(), .

template <std::uint32_t TimerFrequency, std::uint32_t msPeriod, typename ... Subscribers>
class SoftwareTimer 
{
public:
  static void OnTick()
  {
    --ticksRemain ;
    if (ticksRemain == 0U)
    {       
      ticksRemain = ticksReload ;
      (Subscribers::OnTimeout(),...) ;
    }
  }

private:

  static constexpr std::uint32_t msInSec = 1000UL ;
  static constexpr std::uint32_t ticksReload =  
         static_cast<std::uint32_t>((msPeriod * TimerFrequency) / msInSec) ;

  static inline volatile std::uint32_t ticksRemain = ticksReload;
} ;

, 100 ms, 200ms

//   
using Led1Timer = SoftwareTimer<SystemTimerPeriod, 100UL, Led1> ;
using Led2Timer = SoftwareTimer<SystemTimerPeriod, 200UL, Led2> ;
// 
using AppTimerService = TimerService<Led1Timer, Led2Timer> ; 

, Led1 Led2 — GPIOB.6 GPIOC.7

template<typename Pin>
struct Leds
{
  static void OnTimeout()
  {
    //  ,      
    Pin::Toggle(); 
  }
};

template<typename Port, uint32_t num>
struct DummyPin
{
  static void Toggle()
  {
    Port::OCTL::Toggle(1 << num);
  }
};

using Led1 = Leds<DummyPin<GPIOC, 7>>;
using Led2 = Leds<DummyPin<GPIOB, 6>>;

main, ,

int main()
{
  while (true)
  {
    asm volatile(" ");
  }
  return 0;
}

, :

. 1 , OnTick() . , , OnTimeout(), .

, - , RISC-V.

, IAR 1.31 for RISC-V.

ZY RISC-V给人留下了双重印象，一方面是非常可扩展且灵活的事情，您可以做任何事情，另一方面，存在将生产者带到一边的风险，每个人都将自己的花园围起来。我希望所有规范都将很快获得批准，并且一切都会解决。

根据指示进行更正 雷普卡 用名称空间替换了NonVectoredInt结构